What is HDL?

HDL stands for Hardware Description Language. It is a Language that is used to describe the components in designing Hardware. HDL is a programming language that can describe the functionality and timing behavior of the hardware.

So the question.... Why use an HDL?

1. It is becoming very difficult to design directly on hardware.
2. It is easier and cheaper to different design options.
3. Reduce time and cost.

What the Properties of HDL that makes it stand alone?

1. Concurrency

          In computer science, concurrency is a property of systems in which several computations are executing simultaneously, and potentially interacting with each other. The same thing lies with the hardware design of any electronic chip. When we power on the components in the chip have to be activated at a same time. Whereas if we try to design the circuit using a simple C program each line in it will be executed one after another which is sequential line execution which useless in hardware designs.

2. Sequentiality

         Sequentiality is an important property in the hardware design because the chip is made up of numerous modules which have different operation capabilities and these modules operations might be dependent upon various output of primary modules in the design which means there is some dependency on the previous outputs which is nothing but a sequential operation. hence HDL also consists of this kind of property.

3. Timing Analysis

           Static timing analysis (STA) is a method of computing the expected timing of a digital circuit without requiring simulation.

4. Waveform Generation

         HDL also has  the important characteristic of generating the waveform during the simulation process in designing phase.

5. Netlist Generation

          Nets in VLSI are basically the components that are present in the design. HDL generates the list of components that are present in the logic circuit.

There are two types of HDL....

• VHDL ( Very High Speed Integrated Circuit Hardware Description Language)
• Verilog HDL

Both has its own way to design the hardware…Verilog is somewhat easy compared to VHDL but for verification you need to learn a language called System Verilog. VHDL will not allow any silly mistakes whereas Verilog allows and may cause serious mistakes unknowingly. VHDL is so strict like a military conversation…where as Verilog is like a casual talk VHDL is English like one and Verilog looks like C. Requirement or your client interest decides which one to take In a single phrase..Both HDL are Equal ways to reach a destination.