Introduction to Verilog HDL

Verilog is a Hardware Description Language; a textual format for describing electronic circuits and systems. Applied to electronic design, Verilog is intended to be used for verification through simulation, for timing analysis, for test analysis (testability analysis and fault grading) and for logic synthesis.

The Verilog HDL is an IEEE standard - number 1364. The first version of the IEEE standard for Verilog was published in 1995. A revised version was published in 2001; this is the version used by most Verilog users. The IEEE Verilog standard document is known as the Language Reference Manual, or LRM. This is the complete authoritative definition of the Verilog HDL.

A further revision of the Verilog standard was published in 2005, though it has little extra compared to the 2001 standard. SystemVerilog is a huge set of extensions to Verilog, and was first published as an IEEE standard in 2005. See the appropriate Knowhow section for more details about SystemVerilog.

IEEE Std 1364 also defines the Programming Language Interface, or PLI. This is a collection of software routines which permit a bidirectional interface between Verilog and other languages (usually C).

Note that VHDL is not an abbreviation for Verilog HDL - Verilog and VHDL are two different HDLs. They have more similarities than differences, however.

Features of Verilog HDL

• Ability to mix different levels of abstract freely.
• One language for all aspects of design, testing, and verification.
• Verilog has been developed for describing digital circuits and systems.
• Verilog treats a system as black box with an interface.
• The specifications of a system are referred to as Verilog modules.

Levels of Abstraction

1. Behavioral or Algorithmic level

• This is the highest level of abstraction provided by Verilog HDL.
• A module can be implemented in terms of the desired design algorithm without concern for the hardware implementation details.
• Designing at this level is very similar to C programming.

2. Dataflow level

• At this level, the module is designed by specifying the data flow.
• The designer is aware of how data flows between hardware registers and how the data is processed in the design.

3. Gate level

• The module is implemented in terms of logic gates and interconnections between the gates.
• Design at this level is similar to describing a design in terms of a gate-level logic diagram.

4. Switch level

• This is the lowest level of abstraction provided by Verilog.
• A module can be implemented in terms of switches, storage nodes, and the interconnections between them.
• Design at this level requires knowledge of switch-level implementation details.