Synchronous 4 Bit Up counter

VHDL Code:


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;

entity sync_counter is
port(clk,rst,input: in std_logic;
     q : out std_logic_vector(3 downto 0));
end sync_counter;

architecture Behavioral of sync_counter is
signal count : std_logic_vector(3 downto 0);
begin

process (clk,rst,input)

begin

if(rst='0') then
count<="0000";
elsif(clk'event and clk='1') then
if(input='1') then
count<=count + 1;
end if;
end if;
end process;
q<=count;

end Behavioral;

Simulated waveform:

Asynchronus Down counter using T-Flipflops

VHDL Code:

entity down_counter is
port(input,clk,rst: in std_logic;
     q: inout std_logic_vector(2 downto 0));
end down_counter;

architecture Behavioral of down_counter is

component t_ff is
port(clk,rst,t: in std_logic;
     q,qbar: inout std_logic);
end component;

signal w1,w2,w3 : std_logic;

begin

x1: t_ff port map (clk=>clk,rst=>rst,t=>input,q=>q(0),qbar=>w1);
x2: t_ff port map (clk=>q(0),rst=>rst,t=>input,q=>q(1),qbar=>w2);
x3: t_ff port map (clk=>q(1),rst=>rst,t=>input,q=>q(2),qbar=>w3);

end Behavioral;

Note: add the T-flipflop source from the previous post.

Asynchronous Up counter using T- Flipflop

Three-bit counter capable of counting from 0 to 7. The clock inputs
of the three flip-flops are connected in cascade. The T input of each flip-flop is connected
to a constant 1, which means that the state of the flip-flop will be reversed (toggled) at each
positive edge of its clock. We are assuming that the purpose of this circuit is to count the
number of pulses that occur on the primary input called Clock. Thus the clock input of
the first flip-flop is connected to the Clock line. The other two flip-flops have their clock
inputs driven by the Q output of the preceding flip-flop. Therefore, they toggle their state
whenever the preceding flip-flop changes its state from Q = 1 to Q = 0, which results in a
positive edge of the Q signal.

VHDL Code:

 

entity up_counter is
port(input,clk,rst: in std_logic;
     q: inout std_logic_vector(2 downto 0));
end up_counter;

architecture Behavioral of up_counter is

component t_ff is
port(clk,rst,t: in std_logic;
     q,qbar: inout std_logic);
end component;

signal w1,w2,w3 : std_logic;

begin

x1: t_ff port map (clk=>clk,rst=>rst,t=>input,q=>q(0),qbar=>w1);
x2: t_ff port map (clk=>w1,rst=>rst,t=>input,q=>q(1),qbar=>w2);
x3: t_ff port map (clk=>w2,rst=>rst,t=>input,q=>q(2),qbar=>w3);

end Behavioral;

Note: The T-Flipflop program is posted previously add that to the source.

T- Flipflop

The name T flip-flop derives from the behavior of the circuit, which “toggles” its state when T = 1. The toggle
feature makes the T flip-flop a useful element for building counter circuits.

VHDL Code

entity t_ff is
port(clk,rst,t: in std_logic;
     q,qbar: inout std_logic);
end t_ff;

architecture Behavioral of t_ff is

begin
process(clk,rst,t)
begin
if(rst='0') then
q<='0';
elsif(clk'event and clk='1') then
if (t='0') then
q <= q;
else
q <= not q;
end if;
end if;
end process;
qbar<= not q;
end Behavioral;

What is HDL?

HDL stands for Hardware Description Language. It is a Language that is used to describe the components in designing Hardware. HDL is a programming language that can describe the functionality and timing behavior of the hardware.

So the question.... Why use an HDL?

1. It is becoming very difficult to design directly on hardware.
2. It is easier and cheaper to different design options.
3. Reduce time and cost.

What the Properties of HDL that makes it stand alone?

1. Concurrency

          In computer science, concurrency is a property of systems in which several computations are executing simultaneously, and potentially interacting with each other. The same thing lies with the hardware design of any electronic chip. When we power on the components in the chip have to be activated at a same time. Whereas if we try to design the circuit using a simple C program each line in it will be executed one after another which is sequential line execution which useless in hardware designs.

2. Sequentiality

         Sequentiality is an important property in the hardware design because the chip is made up of numerous modules which have different operation capabilities and these modules operations might be dependent upon various output of primary modules in the design which means there is some dependency on the previous outputs which is nothing but a sequential operation. hence HDL also consists of this kind of property.

3. Timing Analysis

           Static timing analysis (STA) is a method of computing the expected timing of a digital circuit without requiring simulation.

4. Waveform Generation

         HDL also has  the important characteristic of generating the waveform during the simulation process in designing phase.

5. Netlist Generation

          Nets in VLSI are basically the components that are present in the design. HDL generates the list of components that are present in the logic circuit.

There are two types of HDL....

• VHDL ( Very High Speed Integrated Circuit Hardware Description Language)
• Verilog HDL

Both has its own way to design the hardware…Verilog is somewhat easy compared to VHDL but for verification you need to learn a language called System Verilog. VHDL will not allow any silly mistakes whereas Verilog allows and may cause serious mistakes unknowingly. VHDL is so strict like a military conversation…where as Verilog is like a casual talk VHDL is English like one and Verilog looks like C. Requirement or your client interest decides which one to take In a single phrase..Both HDL are Equal ways to reach a destination.