Full adder design using Half adder in Verilog

Half adder Verilog code

module halfadder(sum,carry,a,b);
input a,b;
output sum,carry;

xor(sum,a,b);
and(carry,a,b);

endmodule

Full adder using Half adder verilog code

module fulladder(a,b,c,sum,carry);

input a,b,c;

output wire sum, carry;

wire w1,w2,w3;

halfadder h1(.sum(w1),.carry(w2),.a(a),.b(b));

halfadder h2(.sum(sum),.carry(w3),.a(w1),.b(c));

assign carry = w2 | w3;

endmodule