Dataflow modelling in Verilog HDL

A Combinational logic can be modelled using continuous assignment statements.

In complex designs, the number of gates is very large. Currently, automated tools are used to create a gate-level circuit from a Dataflow design description. This process is called Logic Synthesis.

Syntax:

assign [drive_strength] list_of_assignments;

• The continuous assignment creates a continuous relationship between a RHS expression and a LHS net. 
• Continuous assignments can be used instead of primitives. 
• Continuous assignments cannot contain timing controls. 
• You can make an explicit or implicit continuous assignment.

Before getting into the actual dataflow assignments we need to know some of the rules while using this kind of modelling style:

1. The left hand side of an assignment must always be a scalar or vector net. 
2. It cannot be a scalar or vector register.
3. Continuous assignments are always active.
4. The assignment expression is evaluated as soon as one of the right-hand-side operands changes and the value is assigned to the left-hand-side net.
5. The operands on the right-hand side can be registers or nets.

Different Types of Operators

Type of Operators                                              Symbols

Concatenate & Replicate                                      { }   {{ }}

Unary                                                                     !      ~     &     ^     ^~     |

Arithmetic                                                              *     /      %    +     -

Logical shift                                                           <<   >>

Relational                                                              <     <=    >    >=

Equality                                                                  ==   !=   ===  !==

Binary bit-wise                                                      &      ^      ^~     |

Binary logical                                                        &&    ||

Conditional                                                            ? :

Here are some of examples of continuous assignments

wire in_ = ~in; // implicit assignment

wire one = 1'b1; // constant assignment

tri AND = a&b, OR = a|b; // two assignments

assign ab = a & b; // explicit assignment

assign {COUT, SUM} = A + B + CIN ; // assignment to a concatenation

assign o2[7:4] = in[3:0], o2[3:0] = in[7:4]; // part-select

in-depth discussion of each operator will be discussed in the next post