Switch level modelling in verilog

It is also called as the lowest level of abstraction.

The important thing that has to be noted while writing a verilog code in Switch level are the Switch level primitives, which are as follows:

  

                        

                                                                 

       

 Cmos                           nmos                             pmos

Next thing that has to be learned is instantiation of these primitives...

nmos (drain, source, gate);

pmos (drain, source, gate);

cmos  (drain, source, ngate, pgate);

now let us write a Switch level verilog code for a NAND gate.

module nand2_1d (a, b, y); 

input a;

input b;

output y;

supply0 gnd;

supply1 vdd;

wire in1;

      pmos  g1 ( y, vdd, a );

      pmos  g2 ( y, vdd, b );

      nmos  g3 ( y, in1, a );

      nmos  g4 ( in1, gnd, b);

endmodule