Behavioural modelling in Verilog HDL

Behavioural modelling is the highest level of abstraction in the Verilog HDL. Hardware description using behaviour modelling style requires the knowledge of working of that particular device. This modelling looks like a C programming language. In behavioural modelling we are introduced to a new concept called as Procedural block.

Basically Procedural blocks are of two types.  1. Initial block 2. Always block

Initial block and Always block both starts when simulation starts in arbitrary order. The main difference is that initial block executes and stops where as always block is a continuous loop.

Let us see the syntax how it looks like

Initial                                                     always

Begin                                                     Begin

----                                                         -------

----                                                         -------

End                                                        end

Initial block cannot be synthesized where as always blocks can be synthesized hence they are used in main code while initial blocks are used only in testbenches. Inside these blocks there are assignment statements called as Procedural assignments.

There are two types of procedural assignments: Blocking and Non-Blocking assignments.

Blocking assignments: A blocking assignment statements are executed in the order they are specified in a sequential block. The execution of next statement begin only after the completion of the present blocking assignments. A blocking assignment will not block the execution of the next statement in a parallel block. The blocking assignments are made using the operator =.

Let us see this with the help of an example:

initial

begin

    a = 1;

    b = #5 2;

    c = #2 3;

end

In the above example, a  is assigned value 1 at time 0, and b is assigned value 2 at time 5, and c is assigned value 3 at time 7.

Non-blocking assignments: The nonblocking assignment allows assignment scheduling without blocking the procedural flow. The nonblocking assignment statement can be used whenever several variable assignments within the same time step can be made without regard to order or dependence upon each other. Non-blocking assignments are made using the operator <=.

Note: <= is same for less than or equal to operator, so whenever it appears in a expression it is considered to be comparison operator and not as non-blocking assignment.

initial

begin

    a <= 1;

    b <= #5 2;

    c <= #2 3;

end

In the above example, a is assigned value 1 at time 0, and b is assigned value 2 at time 5, and c is assigned value 3 at time 2 (because all the statements execution starts at time 0, as they are non-blocking assignments.

Next type of statements are called as Conditional statements

Conditional statements execute only on a condition.

Types of conditional statements:

1. if and if-else statements

2. case statement

Syntax for if statement

if ( expression )

 statement;

else

 statement;

Example

always @ (a)

begin

if (a==1)

    x = a ;

end

In the above example if a value is equal to 1 then the value of x is updated to the value a i.e. equal to 1.

Case statement syntax

Syntax:  

case ( expression )

case_item ...

endcase

Example

always @ (a,b,c,d,sel)

begin

  case (sel)

3:            y = d;

2:            y = c;

1:             y = b;

  default:  y = a;

  endcase

end

This above example gives the 4x1 multiplexer