Swap / Buffer Circuit

Swap / Buffer circuit can be implemented by using a simple 2X1 Multiplexer.

Swap/Buffer circuit Verilog Code

module swap_buffer(a,b,s,out1,out2);

input a,b,s;

output out1,out2;

mux2x1 m1(.in1(a),.in2(b),.sel(s),.y(out1));

mux2x1 m2(.in1(b),.in2(a),.sel(s),.y(out2));

endmodule

Full adder design using Half adder in Verilog

Half adder Verilog code

module halfadder(sum,carry,a,b);
input a,b;
output sum,carry;

xor(sum,a,b);
and(carry,a,b);

endmodule

Full adder using Half adder verilog code

module fulladder(a,b,c,sum,carry);

input a,b,c;

output wire sum, carry;

wire w1,w2,w3;

halfadder h1(.sum(w1),.carry(w2),.a(a),.b(b));

halfadder h2(.sum(sum),.carry(w3),.a(w1),.b(c));

assign carry = w2 | w3;

endmodule

Behavioural modelling in Verilog HDL

Behavioural modelling is the highest level of abstraction in the Verilog HDL. Hardware description using behaviour modelling style requires the knowledge of working of that particular device. This modelling looks like a C programming language. In behavioural modelling we are introduced to a new concept called as Procedural block.

Basically Procedural blocks are of two types.  1. Initial block 2. Always block

Initial block and Always block both starts when simulation starts in arbitrary order. The main difference is that initial block executes and stops where as always block is a continuous loop.

Let us see the syntax how it looks like

Initial                                                     always

Begin                                                     Begin

----                                                         -------

----                                                         -------

End                                                        end

Initial block cannot be synthesized where as always blocks can be synthesized hence they are used in main code while initial blocks are used only in testbenches. Inside these blocks there are assignment statements called as Procedural assignments.

There are two types of procedural assignments: Blocking and Non-Blocking assignments.

Blocking assignments: A blocking assignment statements are executed in the order they are specified in a sequential block. The execution of next statement begin only after the completion of the present blocking assignments. A blocking assignment will not block the execution of the next statement in a parallel block. The blocking assignments are made using the operator =.

Let us see this with the help of an example:

initial

begin

    a = 1;

    b = #5 2;

    c = #2 3;

end

In the above example, a  is assigned value 1 at time 0, and b is assigned value 2 at time 5, and c is assigned value 3 at time 7.

Non-blocking assignments: The nonblocking assignment allows assignment scheduling without blocking the procedural flow. The nonblocking assignment statement can be used whenever several variable assignments within the same time step can be made without regard to order or dependence upon each other. Non-blocking assignments are made using the operator <=.

Note: <= is same for less than or equal to operator, so whenever it appears in a expression it is considered to be comparison operator and not as non-blocking assignment.

initial

begin

    a <= 1;

    b <= #5 2;

    c <= #2 3;

end

In the above example, a is assigned value 1 at time 0, and b is assigned value 2 at time 5, and c is assigned value 3 at time 2 (because all the statements execution starts at time 0, as they are non-blocking assignments.

Next type of statements are called as Conditional statements

Conditional statements execute only on a condition.

Types of conditional statements:

1. if and if-else statements

2. case statement

Syntax for if statement

if ( expression )

 statement;

else

 statement;

Example

always @ (a)

begin

if (a==1)

    x = a ;

end

In the above example if a value is equal to 1 then the value of x is updated to the value a i.e. equal to 1.

Case statement syntax

Syntax:  

case ( expression )

case_item ...

endcase

Example

always @ (a,b,c,d,sel)

begin

  case (sel)

3:            y = d;

2:            y = c;

1:             y = b;

  default:  y = a;

  endcase

end

This above example gives the 4x1 multiplexer

Dataflow modelling in Verilog HDL

A Combinational logic can be modelled using continuous assignment statements.

In complex designs, the number of gates is very large. Currently, automated tools are used to create a gate-level circuit from a Dataflow design description. This process is called Logic Synthesis.

Syntax:

assign [drive_strength] list_of_assignments;

• The continuous assignment creates a continuous relationship between a RHS expression and a LHS net. 
• Continuous assignments can be used instead of primitives. 
• Continuous assignments cannot contain timing controls. 
• You can make an explicit or implicit continuous assignment.

Before getting into the actual dataflow assignments we need to know some of the rules while using this kind of modelling style:

1. The left hand side of an assignment must always be a scalar or vector net. 
2. It cannot be a scalar or vector register.
3. Continuous assignments are always active.
4. The assignment expression is evaluated as soon as one of the right-hand-side operands changes and the value is assigned to the left-hand-side net.
5. The operands on the right-hand side can be registers or nets.

Different Types of Operators

Type of Operators                                              Symbols

Concatenate & Replicate                                      { }   {{ }}

Unary                                                                     !      ~     &     ^     ^~     |

Arithmetic                                                              *     /      %    +     -

Logical shift                                                           <<   >>

Relational                                                              <     <=    >    >=

Equality                                                                  ==   !=   ===  !==

Binary bit-wise                                                      &      ^      ^~     |

Binary logical                                                        &&    ||

Conditional                                                            ? :

Here are some of examples of continuous assignments

wire in_ = ~in; // implicit assignment

wire one = 1'b1; // constant assignment

tri AND = a&b, OR = a|b; // two assignments

assign ab = a & b; // explicit assignment

assign {COUT, SUM} = A + B + CIN ; // assignment to a concatenation

assign o2[7:4] = in[3:0], o2[3:0] = in[7:4]; // part-select

in-depth discussion of each operator will be discussed in the next post

Switch level modelling in verilog

It is also called as the lowest level of abstraction.

The important thing that has to be noted while writing a verilog code in Switch level are the Switch level primitives, which are as follows:

  

                        

                                                                 

       

 Cmos                           nmos                             pmos

Next thing that has to be learned is instantiation of these primitives...

nmos (drain, source, gate);

pmos (drain, source, gate);

cmos  (drain, source, ngate, pgate);

now let us write a Switch level verilog code for a NAND gate.

module nand2_1d (a, b, y); 

input a;

input b;

output y;

supply0 gnd;

supply1 vdd;

wire in1;

      pmos  g1 ( y, vdd, a );

      pmos  g2 ( y, vdd, b );

      nmos  g3 ( y, in1, a );

      nmos  g4 ( in1, gnd, b);

endmodule

Introduction to Verilog HDL

Verilog is a Hardware Description Language; a textual format for describing electronic circuits and systems. Applied to electronic design, Verilog is intended to be used for verification through simulation, for timing analysis, for test analysis (testability analysis and fault grading) and for logic synthesis.

The Verilog HDL is an IEEE standard - number 1364. The first version of the IEEE standard for Verilog was published in 1995. A revised version was published in 2001; this is the version used by most Verilog users. The IEEE Verilog standard document is known as the Language Reference Manual, or LRM. This is the complete authoritative definition of the Verilog HDL.

A further revision of the Verilog standard was published in 2005, though it has little extra compared to the 2001 standard. SystemVerilog is a huge set of extensions to Verilog, and was first published as an IEEE standard in 2005. See the appropriate Knowhow section for more details about SystemVerilog.

IEEE Std 1364 also defines the Programming Language Interface, or PLI. This is a collection of software routines which permit a bidirectional interface between Verilog and other languages (usually C).

Note that VHDL is not an abbreviation for Verilog HDL - Verilog and VHDL are two different HDLs. They have more similarities than differences, however.

Features of Verilog HDL

• Ability to mix different levels of abstract freely.
• One language for all aspects of design, testing, and verification.
• Verilog has been developed for describing digital circuits and systems.
• Verilog treats a system as black box with an interface.
• The specifications of a system are referred to as Verilog modules.

Levels of Abstraction

1. Behavioral or Algorithmic level

• This is the highest level of abstraction provided by Verilog HDL.
• A module can be implemented in terms of the desired design algorithm without concern for the hardware implementation details.
• Designing at this level is very similar to C programming.

2. Dataflow level

• At this level, the module is designed by specifying the data flow.
• The designer is aware of how data flows between hardware registers and how the data is processed in the design.

3. Gate level

• The module is implemented in terms of logic gates and interconnections between the gates.
• Design at this level is similar to describing a design in terms of a gate-level logic diagram.

4. Switch level

• This is the lowest level of abstraction provided by Verilog.
• A module can be implemented in terms of switches, storage nodes, and the interconnections between them.
• Design at this level requires knowledge of switch-level implementation details. 

What is HDL?

HDL stands for Hardware Description Language. It is a Language that is used to describe the components in designing Hardware. HDL is a programming language that can describe the functionality and timing behavior of the hardware.

So the question.... Why use an HDL?

1. It is becoming very difficult to design directly on hardware.
2. It is easier and cheaper to different design options.
3. Reduce time and cost.

What the Properties of HDL that makes it stand alone?

1. Concurrency

          In computer science, concurrency is a property of systems in which several computations are executing simultaneously, and potentially interacting with each other. The same thing lies with the hardware design of any electronic chip. When we power on the components in the chip have to be activated at a same time. Whereas if we try to design the circuit using a simple C program each line in it will be executed one after another which is sequential line execution which useless in hardware designs.

2. Sequentiality

         Sequentiality is an important property in the hardware design because the chip is made up of numerous modules which have different operation capabilities and these modules operations might be dependent upon various output of primary modules in the design which means there is some dependency on the previous outputs which is nothing but a sequential operation. hence HDL also consists of this kind of property.

3. Timing Analysis

           Static timing analysis (STA) is a method of computing the expected timing of a digital circuit without requiring simulation.

4. Waveform Generation

         HDL also has  the important characteristic of generating the waveform during the simulation process in designing phase.

5. Netlist Generation

          Nets in VLSI are basically the components that are present in the design. HDL generates the list of components that are present in the logic circuit.

There are two types of HDL....

• VHDL ( Very High Speed Integrated Circuit Hardware Description Language)
• Verilog HDL

Both has its own way to design the hardware…Verilog is somewhat easy compared to VHDL but for verification you need to learn a language called System Verilog. VHDL will not allow any silly mistakes whereas Verilog allows and may cause serious mistakes unknowingly. VHDL is so strict like a military conversation…where as Verilog is like a casual talk VHDL is English like one and Verilog looks like C. Requirement or your client interest decides which one to take In a single phrase..Both HDL are Equal ways to reach a destination.