Asynchronus Down counter using T-Flipflops

VHDL Code:

entity down_counter is
port(input,clk,rst: in std_logic;
     q: inout std_logic_vector(2 downto 0));
end down_counter;

architecture Behavioral of down_counter is

component t_ff is
port(clk,rst,t: in std_logic;
     q,qbar: inout std_logic);
end component;

signal w1,w2,w3 : std_logic;

begin

x1: t_ff port map (clk=>clk,rst=>rst,t=>input,q=>q(0),qbar=>w1);
x2: t_ff port map (clk=>q(0),rst=>rst,t=>input,q=>q(1),qbar=>w2);
x3: t_ff port map (clk=>q(1),rst=>rst,t=>input,q=>q(2),qbar=>w3);

end Behavioral;

Note: add the T-flipflop source from the previous post.