Asynchronous Up counter using T- Flipflop

Three-bit counter capable of counting from 0 to 7. The clock inputs
of the three flip-flops are connected in cascade. The T input of each flip-flop is connected
to a constant 1, which means that the state of the flip-flop will be reversed (toggled) at each
positive edge of its clock. We are assuming that the purpose of this circuit is to count the
number of pulses that occur on the primary input called Clock. Thus the clock input of
the first flip-flop is connected to the Clock line. The other two flip-flops have their clock
inputs driven by the Q output of the preceding flip-flop. Therefore, they toggle their state
whenever the preceding flip-flop changes its state from Q = 1 to Q = 0, which results in a
positive edge of the Q signal.

VHDL Code:

 

entity up_counter is
port(input,clk,rst: in std_logic;
     q: inout std_logic_vector(2 downto 0));
end up_counter;

architecture Behavioral of up_counter is

component t_ff is
port(clk,rst,t: in std_logic;
     q,qbar: inout std_logic);
end component;

signal w1,w2,w3 : std_logic;

begin

x1: t_ff port map (clk=>clk,rst=>rst,t=>input,q=>q(0),qbar=>w1);
x2: t_ff port map (clk=>w1,rst=>rst,t=>input,q=>q(1),qbar=>w2);
x3: t_ff port map (clk=>w2,rst=>rst,t=>input,q=>q(2),qbar=>w3);

end Behavioral;

Note: The T-Flipflop program is posted previously add that to the source.