Synchronous 4 Bit Up counter

VHDL Code:


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;

entity sync_counter is
port(clk,rst,input: in std_logic;
     q : out std_logic_vector(3 downto 0));
end sync_counter;

architecture Behavioral of sync_counter is
signal count : std_logic_vector(3 downto 0);
begin

process (clk,rst,input)

begin

if(rst='0') then
count<="0000";
elsif(clk'event and clk='1') then
if(input='1') then
count<=count + 1;
end if;
end if;
end process;
q<=count;

end Behavioral;

Simulated waveform: