Synchronous 4 Bit Up counter

VHDL Code:


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;

entity sync_counter is
port(clk,rst,input: in std_logic;
     q : out std_logic_vector(3 downto 0));
end sync_counter;

architecture Behavioral of sync_counter is
signal count : std_logic_vector(3 downto 0);
begin

process (clk,rst,input)

begin

if(rst='0') then
count<="0000";
elsif(clk'event and clk='1') then
if(input='1') then
count<=count + 1;
end if;
end if;
end process;
q<=count;

end Behavioral;

Simulated waveform:

Asynchronus Down counter using T-Flipflops

VHDL Code:

entity down_counter is
port(input,clk,rst: in std_logic;
     q: inout std_logic_vector(2 downto 0));
end down_counter;

architecture Behavioral of down_counter is

component t_ff is
port(clk,rst,t: in std_logic;
     q,qbar: inout std_logic);
end component;

signal w1,w2,w3 : std_logic;

begin

x1: t_ff port map (clk=>clk,rst=>rst,t=>input,q=>q(0),qbar=>w1);
x2: t_ff port map (clk=>q(0),rst=>rst,t=>input,q=>q(1),qbar=>w2);
x3: t_ff port map (clk=>q(1),rst=>rst,t=>input,q=>q(2),qbar=>w3);

end Behavioral;

Note: add the T-flipflop source from the previous post.

Asynchronous Up counter using T- Flipflop

Three-bit counter capable of counting from 0 to 7. The clock inputs
of the three flip-flops are connected in cascade. The T input of each flip-flop is connected
to a constant 1, which means that the state of the flip-flop will be reversed (toggled) at each
positive edge of its clock. We are assuming that the purpose of this circuit is to count the
number of pulses that occur on the primary input called Clock. Thus the clock input of
the first flip-flop is connected to the Clock line. The other two flip-flops have their clock
inputs driven by the Q output of the preceding flip-flop. Therefore, they toggle their state
whenever the preceding flip-flop changes its state from Q = 1 to Q = 0, which results in a
positive edge of the Q signal.

VHDL Code:

 

entity up_counter is
port(input,clk,rst: in std_logic;
     q: inout std_logic_vector(2 downto 0));
end up_counter;

architecture Behavioral of up_counter is

component t_ff is
port(clk,rst,t: in std_logic;
     q,qbar: inout std_logic);
end component;

signal w1,w2,w3 : std_logic;

begin

x1: t_ff port map (clk=>clk,rst=>rst,t=>input,q=>q(0),qbar=>w1);
x2: t_ff port map (clk=>w1,rst=>rst,t=>input,q=>q(1),qbar=>w2);
x3: t_ff port map (clk=>w2,rst=>rst,t=>input,q=>q(2),qbar=>w3);

end Behavioral;

Note: The T-Flipflop program is posted previously add that to the source.

T- Flipflop

The name T flip-flop derives from the behavior of the circuit, which “toggles” its state when T = 1. The toggle
feature makes the T flip-flop a useful element for building counter circuits.

VHDL Code

entity t_ff is
port(clk,rst,t: in std_logic;
     q,qbar: inout std_logic);
end t_ff;

architecture Behavioral of t_ff is

begin
process(clk,rst,t)
begin
if(rst='0') then
q<='0';
elsif(clk'event and clk='1') then
if (t='0') then
q <= q;
else
q <= not q;
end if;
end if;
end process;
qbar<= not q;
end Behavioral;

VLSI Design Unit - III

VLSI Design unit - 1

VLSI Design Unit - II