CMOS Inverter using Verilog Switch level modelling

Truth Table:

a	F
0	1
1	0

module cmos_inv(f,a);

//declaring the input and output variables

input a;                //'a' is the input and 'f' is the output

output f;

//syntax for declaring the power supply and ground

supply1 vdd;

supply0 gnd;

//instantiating pmos and nmos transistors (drain,source,gate)

pmos p1(f,vdd,a);

nmos n1(f,gnd,a);

endmodule